HDM8515 Datasheet, PDF (5/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

LIST OF FIGURES
FIGURE 1: TOP LEVEL BLOCK DIAGRAM....................................................................................................................7
FIGURE 2: INPUT DATA TIMING DIAGRAM .............................................................................................................10
FIGURE 3: INTEL 80C88A READ TIMING DIAGRAM............................................................................................... 11
FIGURE 4: INTEL 80C88A WRITE TIMING DIAGRAM............................................................................................. 12
FIGURE 5: INTEL 8051 READ TIMING DIAGRAM .....................................................................................................13
FIGURE 6: INTEL 8051 WRITE TIMING DIAGRAM...................................................................................................14
FIGURE 7: MOTOROLA READ TIMING DIAGRAM....................................................................................................15
FIGURE 8: MOTOROLA WRITE TIMING DIAGRAM.................................................................................................16
FIGURE 9: OUTPUT TIMING DIAGRAM FOR NORMAL PARALLEL....................................................................... 17
FIGURE 10: OUTPUT TIMING DIAGRAM FOR NORMAL SERIAL ...........................................................................17
FIGURE 11: OUTPUT TIMING DIAGRAM FOR REGULATED PARALLEL............................................................... 18
FIGURE 12: OUTPUT TIMING DIAGRAM FOR REGULATED SERIAL.....................................................................18
FIGURE 13: ADC BLOCK DIAGRAM............................................................................................................................ 20
FIGURE 14 DEMODULATOR BLOCK DIAGRAM........................................................................................................ 21
FIGURE 15: NOISE MEASUREMENT CIRCUIT ...........................................................................................................23
FIGURE 16: NOISE ACCUMULATOR AS A FUNCTION OF SNR AND TIME............................................................ 24
FIGURE 17: VITERBI DECODER...................................................................................................................................25
FIGURE 18: REED SOLOMON DECODER.................................................................................................................... 29
FIGURE 19: TYPICAL SET TOP BOX DEMODULATOR............................................................................................ 35
FIGURE 20: MECHANICAL CONFIGURATION ...........................................................................................................38
FIGURE 21: MECHANICAL CONFIGURATION ...........................................................................................................40
FIGURE 22:ANALOG PIN CONNECTION.................................................................................................................... 41
FIGURE 23: CLOCK GENERATION CIRCUIT...........................................................................................................41
FIGURE 24: I2C WRITE TO THE HDM8515..............................................................................................................46
FIGURE 25: I2C READ FROM THE HDM8515............................................................................................................47
FIGURE A1: SYMBOL TIMING RECOVERY TRANSIENT RESPONSE....................................................................... 67
FIGURE A2: CARRIER PHASE RECOVERY TRANSIENT RESPONSE ........................................................................ 68
FIGURE A3: CARRIER PHASE RECOVERY TRANSIENT RESPONSE WITH LOW SNR ..........................................69
FIGURE A4: ADJACENT CHANNEL INTERFERENCE OF 10 DB, 1.35 SPACING.................................................... 72
FIGURE A5: PERFORMANCE WITH INTERFERER AT DIFFERENT CARRIER SPACINGS .....................................73
FIGURE A6: PERFORMANCE WITH +10 DB INTERFERER......................................................................................74
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