HDM8515 Datasheet, PDF (17/75 Pages) Hynix Semiconductor – DVB/DSS Compliant Receiver

Table 11: Output Timing
Symbol
Parameter
Min.
Max.
Unit
tsu Output Data Setup before DATA_CLK and DATA_STB
5
-
ns
thd
Output Data Hold after DATA_CLK and DATA_STB
10
-
ns
DATA_CLK
t_su
t _hd
DATA_STB
FRAME_SYNC
DATA_VALID
DATA
n-3 n-2 n-1 n xx xx xx xx xx xx xx xx xx 1 2 3 4
DATA_CLK
DATA_STB
FIGURE 9: OUTPUT TIMING DIAGRAM FOR NORMAL PARALLEL
t_su
t _hd
FRAME_SYNC
DATA_VALID
DATA[0] ^{8n-8 xx xx 8n-7 8n-6 8n-5 8n-4 xx 8n-3 8n-2 8n-1 8n xx 1 2 3 4}
FIGURE 10: OUTPUT TIMING DIAGRAM FOR NORMAL SERIAL
NOTE : In case of DVB, n is 188
In case of DSS, n is 144
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