HMT351U6AFR8C-G7 Datasheet, PDF (44/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
DDR3 1333 Speed Bin
CL - nRCD - nRP
Parameter
Internal read
command to first
Symbol
t_AA
ACT to internal read
or write delay time
t_RCD
PRE command period t_RP
ACT to ACT or REF
command period
t_RC
ACT to PRE
command period
t_RAS
CWL = 5 t_CK(AVG)
CL = 5
CWL = 6, 7 t_CK(AVG)
CWL = 5 t_CK(AVG)
CL = 6 CWL = 6 t_CK(AVG)
CWL = 7 t_CK(AVG)
CWL = 5 t_CK(AVG)
CL = 7 CWL = 6 t_CK(AVG)
CWL = 7 t_CK(AVG)
CWL = 5 t_CK(AVG)
CL = 8 CWL = 6 t_CK(AVG)
CWL = 7 t_CK(AVG)
CWL = 5, 6 t_CK(AVG)
CL = 9
CWL = 7 t_CK(AVG)
CWL = 5, 6 t_CK(AVG)
CL = 10
CWL = 7 t_CK(AVG)
Supported CL Settings
Supported CWL Settings
Rev. 0.02 / Apr 2009
DDR3-1333H
min
13.125
9-9-9
max
20
13.125
—
13.125
—
49.125
—
36
2.5
1.875
1.875
1.5
1.5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(Optional)
6, 7, 8, 9
5, 6, 7
9 * tREFI
3.3
< 2.5
< 2.5
<1.875
<1.875
Unit Note
ns
ns
ns
ns
ns
ns 1,2,3,4,7
ns
4
ns 1,2,3,7
ns 1,2,3,4,7
ns
4
ns
4
ns 1,2,3,4,7
ns 1,2,3,4
ns
4
ns 1,2,3,7
ns 1,2,3,4
ns
4
ns 1,2,3,4
ns
4
ns
1,2,3
ns
5
n_CK
n_CK
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