HMT351U6AFR8C-G7 Datasheet, PDF (35/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
Table 3 - IDD0 Measurement-Loop Pattern^a)
Data^b)
00
ACT 0 0 1 1 0 0 00 0 0 0 0
-
1,2
D, D 1 0 0 0 0 0 00 0 0 0 0
-
3,4
D, D 1 1 1 1 0 0 00 0 0 0 0
-
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE 0 0 1 0 0 0 00 0 0 0 0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT 0 0 1 1 0 00 00 0 0 F 0
-
...
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0
-
...
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.02 / Apr 2009
35