HMT351U6AFR8C-G7 Datasheet, PDF (14/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
4. Address Mirroring Feature
There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control
lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of
the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3
modules, a scheme was defined to reduce the length of these traces.The pins on the SDRAM are defined in a manner
that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins,
do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are
address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are
wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the
Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.
4.1 DRAM Pin Wiring for Mirroring
Connector Pin
A3
A4
A5
A6
A7
A8
BA0
BA1
Rank 0
A3
A4
A5
A6
A7
A8
BA0
BA1
SDRAM Pin
Rank 1
A4
A3
A6
A5
A8
A7
BA1
BA0
<Table 4.1: SDRAM Pin Wiring for Mirroring >
The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case.
The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well.
Rev. 0.02 / Apr 2009
14