HMT351U6AFR8C-G7 Datasheet, PDF (15/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
No Mirroring
Mirroring
< Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses >
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is
read the same way. There are limitations however. When writing to the internal registers with a "load mode" opera-
tion, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a
few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement
that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been
designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller
must read the SPD and have the capability of de-mirroring the address when accessing the second rank.
Rev. 0.02 / Apr 2009
15