HMT351U6AFR8C-G7 Datasheet, PDF (21/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
Part B: H old
Delta TRH
vIH (AC)m in
vIH (D C)m in
vRefDQ or
vRefCA
vIL(DC)m ax
D elta TFH
vIL(AC)m ax
< Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >
6.3.2 Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table
and Figure .
Description
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
Measured
Min
Max
VILdiffmax
VIHdiffmin
VIHdiffmin
VILdiffmax
Defined by
VIHdiffmin-VILdiffmax
DeltaTRdiff
VIHdiffmin-VILdiffmax
DeltaTFdiff
Note:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Rev. 0.02 / Apr 2009
21