HMT351U6AFR8C-G7 Datasheet, PDF (22/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
D e lta
T R d iff
vIH diffm in
0
D e lta
TFdiff
vILdiffm ax
< Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >
6.4 DC & AC Output Buffer Levels
6.4.1 Single Ended DC & AC Output Levels
Below table shows the output levels used for measurements of single ended signals.
Symbol
Parameter
VOH(DC) ^{DC output high measurement level}
(for IV curve linearity)
DDR3-1066, 1333
0.8 x VDDQ
Unit
V
Notes
VOM(DC) ^{DC output mid measurement level}
(for IV curve linearity)
VOL(DC) ^{DC output low measurement level}
(for IV curve linearity)
VOH(AC) ^{AC output high measurement level}
(for output SR)
0.5 x VDDQ
0.2 x VDDQ
VTT + 0.1 x VDDQ
V
V
V
1
VOL(AC) ^{AC output low measurement level}
VTT - 0.1 x VDDQ
V
1
(for output SR)
1. The swing of ‚ 1 x VDDQ is based on approximately 50% of the static single ended output high or low swing
with a driver impedance of 40ʃ and an effective test load of 25ʃ to VTT = VDDQ / 2.
Rev. 0.02 / Apr 2009
22