HMT351U6AFR8C-G7 Datasheet, PDF (20/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
6.3 Slew Rate Definitions
6.3.1 For Single Ended Input Signals
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef
and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VRef and the first crossing of VIL(AC)max.
- Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and
the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of VIH(DC)min and the first crossing of VRef.
Description
Input slew rate for rising edge
Input slew rate for falling edge
Input slew rate for rising edge
Input slew rate for falling edge
Measured
Min
Max
Vref
VIH(AC)min
Vref
VIL(AC)max
VIL(DC)max
Vref
VIH(DC)min
Vref
Defined by
VIH(AC)min-Vref
Delta TRS
Vref-VIL(AC)max
Delta TFS
Vref-VIL(DC)max
Delta TFH
VIH(DC)min-Vref
Delta TRH
< Table 6.3.1: Single-Ended Input Slew Rate Definition >
Applicable for
Setup
(tIS, tDS)
Hold
(tIH, tDH)
Part A: Set up
Rev. 0.02 / Apr 2009
Delta TFS
Delta TRS
vIH(AC)min
vIH(DC)min
vRefDQ or
vRefCA
vIL(DC)max
vIL(AC)max
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