HMT351U6AFR8C-G7 Datasheet, PDF (43/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC
for each corresponding bin
DDR3 1066 Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command to
first data
t_AA
ACT to internal read or
write delay time
t_RCD
PRE command period
t_RP
ACT to ACT or REF
command period
t_RC
ACT to PRE command
period
t_RAS
CL = 5
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 6
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 7
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 8
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.125
DDR3-1066F
7-7-7
max
20
13.125
—
13.125
—
50.625
—
37.5
2.5
1.875
1.875
9 * tREFI
Reserved
Reserved
Reserved
Reserved
Reserved
6, 7, 8
5, 6
3.3
< 2.5
< 2.5
Unit Note
ns
ns
ns
ns
ns
ns 1)2)3)4)6)
ns 4)
ns 1)2)3)6)
ns 1)2)3)4)
ns 4)
ns 1)2)3)4)
ns 4)
ns 1)2)3)
n_CK
n_CK
Rev. 0.02 / Apr 2009
43