HMT351U6AFR8C-G7 Datasheet, PDF (31/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6AFR8C
HMT351U7AFR8C
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
t_CK
CL
n_RCD
n_RC
n_RAS
n_RP
n_FAW
n_RRD
n_RFC -512Mb
n_RFC-1 Gb
n_RFC- 2 Gb
n_RFC- 4 Gb
n_RFC- 8 Gb
x4/x8
x16
x4/x8
x16
DDR3-1066
7-7-7
1.875
7
7
27
20
7
20
27
4
6
48
59
86
160
187
DDR3-1333
9-9-9
1.5
9
9
33
24
9
20
30
4
5
60
74
107
200
234
Unit
ns
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: High
between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on
I_DD0
page 30; Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... (see Table 3 on page 30); Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal:
stable at 0; Pattern Details: see Table 3 on page 30
Operating One Bank Active-Precharge Current
I_DD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS:
High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling
according to Table 4 on page 31; DM: stable at 0; Bank Activity: Cycling with on bank active at a time:
0,0,1,1,2,2,... (see Table 4 on page 31); Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal:
stable at 0; Pattern Details: see Table 4 page 31
Rev. 0.02 / Apr 2009
31