HMT351U6AFR8C-G7 Datasheet, PDF (18/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

voltage
V_Ref(DC)
V_Ref ac-noise
HMT351U6AFR8C
HMT351U7AFR8C
VDD
V_Ref(t)
V_Ref(DC)max
VDD/2
V_Ref(DC)min
VSS
time
< Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits >
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on
VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1
This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low
level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account
for VRef(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associ-
ated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD)
are included in DRAM timings and their associated deratings.
6.2.2 DC & AC Logic Input Levels for Differential Signals
Symbol
Parameter
DDR3-1066, DDR3-1333
Min
Max
VIHdiff
VILdiff
Differential input logic high
Differential input logic low
+ 0.200
-
- 0.200
Note1:
Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page
Unit Notes
V
1
V
1
Rev. 0.02 / Apr 2009
18