HMT351U6AFR8C-G7 Datasheet, PDF (38/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

Table 7 - IDD4R and IDDQ24RMeasurement-Loop Pattern^a)
HMT351U6AFR8C
HMT351U7AFR8C
Data^b)
00
1
2,3
4
5
6,7
1 8-15
2 16-23
3 24-31
4 32-39
5 40-47
6 48-55
7 56-63
RD 0 1 0
1
0
0 00 0
0
0
0
000000
00
D 1 0 0 0 0 0 00 0 0 0 0
-
D,D 1 1 1 1 0 0 00 0 0 0 0
-
RD 0 1 0
1
0
0 00 0
0
F
0
001100
11
D 1 0 0 0 0 0 00 0 0 F 0
-
D,D 1 1 1 1 0 0 00 0 0 F 0
-
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.02 / Apr 2009
38