HD66108 Datasheet, PDF (9/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
Register List
Reg. No. _{Reg. Register Read/}
Data Bit Assignment
CS RS 2 1 0 Symbol Name Write 7 6 5 4 3 2 1 0 Busy Time Notes
1 — ————
Invalid —
—
1
0 0 — — — AR
Address R
W
0 1 0 0 0 DRAM Display R
memory _W
0 1 0 0 1 XAR
X
R
address _W
0 1 0 1 0 YAR
Y
R
address _W
0 1 0 1 1 FCR Control R
W
0 1 1 0 0 MDR Mode R
W
0 1 1 0 1 CSR C select R
W
0 1 110—
Invalid —
Busy STBY DISP
Register No. None
D7 D6 D5 D4 D3 D2 D1 D0
XAD
YAD
INC WLS PON ROS
DUTY
8 clocks max 2
3
None
1.5 clocks max
None
1.5 clocks max
None
FFS
DWS None
EOR
CLN
None
—
0 1 111—
Invalid —
—
Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Reading
these bits returns 0.
2. DRAM is not actually a register but can be handled as one.
3. Setting the WLS bit of control register to 1 invalidates D7 and D6 bits of the display memory
register.
4. DRAM must not be written to or read from until a time period of t_CL1 has elapsed rewriting the
DUTY bit of FCR or the FFS bit of MDR. t_CL1 can be obtained from the following equation; in
general, a time period of 1 ms or greater is sufficient if the frame frequency is 60–90 Hz.
t_{CL1 =}
D2
(ms) ................ Equation
Ni·f_CLK(kHz)
D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36)
128 (duty = 1/48 or 1/50)
96 (duty = 1/64 or 1/66)
Ni (frequency-division ratio specified by the mode register’s FFS bits):
2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8
Refer to “6. Clock and Frame Frequency.”
f_CLK: Input clock frequency (kHz)
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