HD66108 Datasheet, PDF (19/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
(4) Limitations on Access
As shown in Figure 9, the display memory must not be rewritten until a time period of t_CL1 or longer
has elapsed after rewriting the control register’s DUTY bits or the mode register’s FFS bits. However,
display memory and registers other than the control register and mode register can be accessed even
during this time period. t_CL1 can be obtained from the following equation. If using an LSI with a frame
frequency of 60 Hz or greater, a time period of 1 ms should be sufficient.
t_CL1=
D2
(ms) ...... Equation 1
Ni·f_CLK(kHz)
D2 (duty correction value):
192 (duty = 1/32, 1/34, or 1/36)
128 (duty = 1/48 or 1/50)
96 (duty = 1/64 or 1/66)
Ni (frequency-division ratio specified by the mode register’s FFS bits):
2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8
f_CLK: Input clock frequency (kHz)
3.2 X and Y address Counter Auto-Incrementing Function
As described in “2. Display Memory Construction and Word Length Setting,” the HD66108T display
memory has X and Y addresses. Internal X address counter and Y address counter both employ an auto-
incrementing function. After display data is read or written, the X or Y address is incremented according
to the address increment direction selected by internal register.
Although X addresses up to 20 are valid when 8 bits make up one word (up to 27 when 6 bits make up
one word), the X address counter can count up to 31 since it is a 5-bit free counter. Similarly, although Y
addresses up to 64 are valid, the Y address counter can count up to 127. Consequently, X or Y address
must be reset at an appropriate point as shown in Figure 10.
Rewriting DUTY or FFS bits
Accessing other registers
t_CL1 or longer
Rewriting display memory
Figure 9 Rewriting Display Memory after Rewriting Registers
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