HD66108 Datasheet, PDF (47/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
6. Mode Register (MDR) (Accessed with RS = 1, Register Number = (B’100)
This register (Figure 32), containing 3 invalid bits (D7 to D5) and 5 valid bits (D4 to D0), selects a
system clock and type of LCD driving waveform. It must also be initialized after power-on since it
determines overall HD66108T operation like the FCR register. If the FFS bits are rewritten after
initialization at power-on (if values other than the initial values are desired), the display memory will not
preserve data; the display memory must be set again after a time period of t_CL1 or longer. For determining
t_CL1, refer to equation 1 in section 3.1).
D7 D6 D5 D4 D3 D2 D1 D0
—
FFS
DWS
(1) FFS (frame frequency select)
Bit
No. 4 3 2
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
Frequency-
Division Ratio
1
1/2
1/3
1/4
1/6
1/8
2
—
(2) DWS (LCD driving waveform select)
Bit
No. 1 0
0 00
1 01
2 10
3 11
Driving Waveform
A-type waveform
B-type waveform
C-type waveform
—
Figure 32 Mode Register
1000