HD66108 Datasheet, PDF (17/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
(2) Busy Check
A busy time period appears after display memory read/write or X or Y address register write, since
post-access processing is performed synchronously with internal clock pulses. Updating data in
registers other than the address register is disabled during this time. Subsequent data must be input
after confirming ready mode by reading the address register. The busy time period is a maximum of 8
clock pulses after display memory read/write and a maximum of 1.5 clock pulses after X or Y address
register write (Figure 7).
HD66108T
OSC
BUSY
FLAG
Ready
Internal
operation
CPU
WR
Busy 8 clock pulses max
Operates internally
Ready
RD
RS
DB7
Figure 7 Relationship between Clock Pulses and Busy Time (Updating Display Data)
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