HD66108 Datasheet, PDF (40/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
9. Multi-Chip Operation
Using multiple HD66108T chips (= multi-chip operation) provides the means for extending the number
of display dots. Note the following items when using the multi-chip operation.
(1) The master chip and the slave chips must be determined; the /S pin of the master chip must be set
low and the /S pin of the slave chips must be set high.
(2) All the HD66108T chips will be slave chips if HD61203 or its equivalent is used as a row driver.
(3) The master chip supplies the FLM, CL1, and M signals to the slave chips via the corresponding pins,
which synchronizes the slave chips with the master chip.
(4) Since a master chip outputs synchronization signals, all data registers must be set.
(5) The following bits for slave chips must always be set:
INC, WLS, PON, and ROS (control register) FFS (mode register)
It is not necessary to set the control register’s DUTY bits, the mode register’s DWS bits, or the C
select register. For other registers’ settings, refer to Table 6.
(6) All chips must be set to LCD off in order to turn off the display.
(7) The standby function of slave chips must be started up first while that of the master chip must be
terminated first.
Figure 24 to 26 show the connections of the synchronization signals for different system configurations
and Table 6 lists the differences between master mode and slave mode.
Table 6 Comparison between Master and Slave Mode
Item
Master Mode
Pin:
0/S
Must be set low
OSC1, OSC2 Oscillation is possible
CO
= OSC1
FLM, CL1, M
Output signals
Register: AR
Valid
XAR
Valid
YAR
Valid
FCR
Valid
MDR
Valid
CSR
Valid (only if the DWS bits are set for
the C-type waveform)
Notes: Valid: Needs to be set
Invalid: Needs not be set
Slave Mode
Must be set high
Oscillation is possible
= OCS1
Input signals
Valid
Valid
Valid
Valid except for the DUTY bits
Valid except for the DWS bits
Invalid
993