HD66108 Datasheet, PDF (58/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
AC Characteristics (2) (V_CC = 2.7 to 4.5V, GND = 0V, Ta = –20 to +75°C, unless otherwise noted)
1. CPU Bus Timing (Figure 37)
Item
Symbol Min
5' high-level pulse width
t_WRH
1.0
5' low-level pulse width
t_WRL
1.0
:5 high-level pulse width
t_WWH
1.0
:5low-level pulse width
t_WWL
1.0
– :5 5' high-level pulse width
t_WWRH
1.0
&6 RS setup time
t_AS
0.5
&6 RS hold time
t_AH
0.1
Write data setup time
t_DSW
1.0
Write data hold time
t_DHW
0
Read data output delay time
t_DDR
—
Read data hold time
t_DHR
20
External clock cycle time
t_CYC
1.6
External clock high-level pulse width t_WCH
0.7
External clock low-level pulse width
t_WCL
0.7
External clock rise and fall time
t_r, t_f
—
Note: Measured by test circuit 2 (Figure 39).
Max
—
—
—
—
—
—
—
—
—
0.5
—
5.0
—
—
0.1
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Note
ns
Note
µs
µs
µs
µs
2. LCD Interface Timing (Figure 38)
Item
Symbol
Min
Max
Unit
Notes
0/S = 0 CL1 High-level pulse width t_WCH1
35
—
µs
1, 4
CL1 Low-level pulse width t_WCL1
35
—
µs
1, 4
FLM Delay time
t_DFL1
–2.0
+2.0
µs
4
FLM Hold time
t_HFL1
–2.0
+2.0
µs
4
M output delay time
t_DMO1
–2.0
+2.0
µs
4
0/S = 1 CL1 High-level pulse width t_WCH2
35
—
µs
4
CL1 Low-level pulse width t_WCL2
11 × t_CYC
—
µs
2, 4
FLM Delay time
t_DFL2
–2.0
1.5 × t_CYC
µs
3, 4
FLM Hold time
t_HFL2
–2.0
+2.0
µs
4
M delay time
t_DMI
–2.0
+2.0
µs
4
Notes: 1. When R_OSC is 91 kΩ (V_CC = 4.0 to 6V) or 75 kΩ (V_CC = 2.7 to 4.0V) and bits FFS are set for 1.
2. When bits FFS are set for 1 or 2. The value is 19 × t_CYC in other cases.
3. When bits FFS are set for 1 or 2. The value is 8.5 × t_CYC in other cases.
4. Measured by test circuit 2 (Figure 39).
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