HD66108 Datasheet, PDF (14/60 Pages) Hitachi Semiconductor – (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)

HD66108
2. Display Memory Construction and Word Length Setting
The HD66108T has a bit-mapped display memory of 165 × 65 bits. As shown in Figure 4, data from the
MPU is stored in the display memory, with the MSB (most significant bit) on the left and the LSB (least
significant bit) on the right.
The sections on the LCD panel corresponding to the display memory bits in which 1’s are written will be
displayed as on (black).
Display area size of the internal RAM is determined by control register (FCR) settings (refer to Table 1).
The start address in the Y direction for the display area is always Y0, independent of the register setting.
In contrast, the start address in the X direction is X0 in the modes for 165-column-output, 65-row-output
from the right side, and 33-row-output from the right side, and is X32 in the 65-row-output mode from
the left and right sides.
Each display area contains the number of dots shown in Table 1, beginning from each start address.
For more detail, refer to “4.2 Row Output Data Setting,” Figures 15 to 19.
In the display memory, one X address is assigned to each word of 8 or 6 bits long in X direction. (Either
8 or 6 bits can be selected as word length of display data.) Similarly, one Y address is assigned to each
row in Y direction.
Accordingly, X address 20 in the case of 8-bit word and X address 27 in the case of 6-bit word have 5 and
3 bits of display data, respectively. Nevertheless, data is also stored here with the MSB on the left (Figure
5).
COM1
COM2
Display on
165 × 65-dot LCD
COM65
X0 X1 X2 X3 X4 X5 X6 X7
X164
Y0 _{1 0 1 0 0 1 0 1}
DB7
(MSB)
DB0
(LSB)
156 × 65-bit
display memory
Y64
Figure 4 Relationship between Memory Construction and Display
967