MB85RQ4MLPF-G Datasheet, PDF (9/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After driving CS low,
op-code of WRSR and 8 writing data bits are input to SI, and then driving CS high. QPI mode bit is not able to be
written with WRSR command. A SI value corresponding to bit 6 is ignored. Bit 4 and Bit 5 shall be set to “0”. WEL
(Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is
ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0
is ignored. The WP signal level shall be fixed before performing WRSR command, and not be changed until
the end of command sequence. The maximum clock frequency for the WRSR command is 108 MHz.
CS
SCK
SI
SO
012345670 1 2 3 4 5 6 7
Data In
0000000176543210
MSB
LSB
High-Z
DS501-00043-2v0-E
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