MB85RQ4MLPF-G Datasheet, PDF (12/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• RDID
The RDID command reads fixed Device ID. After driving CS low, RDID op-code is input to SI and more 32
clock cycles are input to SCK, and then driving CS high. The SI value is invalid during this time. SO is output
synchronously to a falling edge of SCK. The output order is: Manufacturer ID (8bit)/Continuation code (8bit)/
Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit
in 32-bit Device ID until CS is risen. The maximum clock frequency for the RDID command is 108 MHz.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11
31 32 33 34 35 36 37 38 39
SI
10011111
Invalid
High-Z
SO
Data Out
31 30 29 28
MSB
Data Out
876543210
LSB
Manufacturer ID
Continuation code
bit
7654321
0000010
0111111
Proprietary use
Product ID (1st Byte) 0 0 1 0
Density
100
Proprietary use
Product ID (2nd Byte) 1 0 0 0 0 1 0
0 Hex
0 04H Fujitsu
1 7FH
Hex
1 29H Density: 01001B = 4 Mbit
Hex
1 85H
■ LC MODE
The following read commands have a variable latency period between the end of mode bit and the beginning
of read data.
• FRQO
• FRQAD
This nonvolatile configuration bit (LC1, LC0) sets the number of dummy cycles(= latency period) to be used
in advance, therefore MB85RQ4ML can start to read immediately with an appropriate dummy cycles.
Dummy Cycles vs. SCK Frequency
LC1 LC0 Number of Dummy Cycles Frequency Limit of SCK (MHz)
0
0
6 (Default)
108
0
1
4
78
1
0
2
46
1
1
0
15
12
DS501-00043-2v0-E