MB85RQ4MLPF-G Datasheet, PDF (18/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
■ QPI MODE COMMAND
QPI Mode can shorten op-code input cycle from 8 cycles to 2 cycles with 4 I/O pins. The device enters QPI
Mode with the EQPI Command. When in QPI Mode, the Status Register bit 6 is set to “1” and will reset to
“0” either when the device exits from the QPI Mode with the DQPI command or at power-off. After power-
on, QPI mode is disabled.
Mode Name
The command list supported in QPI mode
Description
Op-code Max Freq. (MHz) QPI
XIP
WREN Set Write Enable Latch
0000 0110B
108
Yes
No
SPI WRDI Reset Write Enable Latch
0000 0100B
108
Yes
No
RDSR Read Status Register
0000 0101B
108
Yes
No
Quad ^{FRQAD Fast Read Quad Address and Data 1110 1011B}
SPI _{WQAD Write Quad Address and Data}
0001 0010B
108*
108
Yes
Yes
Yes
No
QPI DQPI Disable QPI mode
1111 1111B
108
Yes
No
*: The frequency when the number of dummy cycles is default value of 6 (see “■ LC MODE”).
• EQPI (Enable QPI mode)
The EQPI command is used for the device to enter QPI mode, at a maximum frequency of 108 MHz.
After driving CS low, the op-code is input to SI(IO0). The command is terminated by driving CS high. When
in QPI Mode, the Status Register bit 6 is set to “1” and the device stays in QPI mode until power-off or the
DQPI command is issued.
CS
SCK
SI
01234567
OPCODE
00111000
EQPI Command Sequence
18
DS501-00043-2v0-E