MB85RQ4MLPF-G Datasheet, PDF (8/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• RDSR
The RDSR command reads status register data. After driving CS low, op-code of RDSR is input to SI and
more 8-cycle clock is input to SCK, and then driving CS high. The SI value is invalid for this time. SO is
output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register
is enabled by sending SCK continuously before rising of CS. The maximum clock frequency for the RDSR
command is 108 MHz.
CS
SCK
0 1 2 3 4 5 6 70 1 2 3 4 5 6 7
SI
00000101
SO
High-Z
MSB
Invalid
Data Out
RDSR Command Sequence
Invalid
LSB
CS
SCK
IO0
IO1
IO2
IO3
0123456789
OPCODE
01
0076
MSB
01
00
High-Z
Data out
5 4 32
High-Z
High-Z
10
LSB
RDSR Command Sequence (QPI mode)
8
DS501-00043-2v0-E