MB85RQ4MLPF-G Datasheet, PDF (20/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
■ BLOCK PROTECT
Writing protect block for WRITE, WQD and WQAD commands are configured by the value of BP0 and BP1
in the status register.
BP1
0
0
1
1
BP0
0
1
0
1
Protected Block
None
60000H to 7FFFFH (upper 1/4)
40000H to 7FFFFH (upper 1/2)
00000H to 7FFFFH (all)
■ WRITING PROTECT
Writing operation of WRITE, WQD, WQAD and the WRSR commands are protected with the value of WEL,
WPEN, WP as shown in the table.
WEL
WPEN
WP
Protected Blocks Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
■ HOLD OPERATION
Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for
starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is
transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level
when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case
the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”
level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.
And, SO becomes High-Z while reading command (RDSR, READ, FSTRD). If CS is rising during hold status,
a command is aborted. In case the command is aborted before its recognition, WEL holds the value before
transition to hold status.
Note: The HOLD operation is disabled during Quad SPI Mode (FRQO, FRQAD, WQD, WQAD) and QPI mode.
CS
SCK
HOLD
20
Hold Condition
Hold Condition
DS501-00043-2v0-E