MB85RQ4MLPF-G Datasheet, PDF (13/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
■ QUAD SPI MODE COMMAND
• FRQO (Fast Read Quad Output)
The FRQO command is similar to the FSTRD command, except that the data is shifted out 4 bits at one time
using 4 I/O pins (IO0 (SI), IO1 (SO), IO2 (WP) and IO3 (HOLD)) instead of 1 bit, at a maximum frequency
of 108 MHz. The data transfer rate of the FRQO command is four times higher than the FSTRD command.
After driving CS low, FRQO op-code and arbitrary 24 address bits are input to IO0. The 5 upper address
bits are ignored. Then 8 mode bits are input to 4 I/O pins for 2 cycles, followed by dummy cycles. The number
of dummy cycles is defined beforehand by the frequency of SCK, and configured by the latency bit of LC1
and LC0. The op-code, the address and the mode bits are latched on the rising edge of SCK. After that,
FRAM memory cell array data are shifted out 4 bits at one time through 4 I/O pins synchronously to the
falling edge of SCK. When CS is risen, the FRQO command is completed, otherwise it keeps on reading
with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 2 cycles
before CS rising. When it reaches the most significant address, it rolls over to the starting address, and
reading cycle keeps on infinitely.
Address jumps can be done without the need for additional FRQO command. This is controlled through the
setting of the Mode bits after the address sequence. This added feature, which is called “XIP mode”, removes
the need for the command sequence. If the Mode bits equal EFH or AFH, then the device remains in FRQO
mode and the next address can be entered (after CS is raised high and then asserted low) without requiring
the FRQO command, thus eliminating 8 cycles for the command sequence. If the Mode bits are any value
other than EFH and AFH, then the next time CS is raised high the device will be released from FRQO mode.
After that, the device can accept SPI commands. CS should not be driven high during mode or dummy bits
as this may make the mode bits indeterminate.
It is important that the I/O pins are set to high-impedance prior to the falling edge of the first data out clock.
The FRQO command is terminated by driving CS high at any time during data output.
CS
SCK
IO0
IO1
IO2
IO3
IO switches from Input to Output
嵣嵣嵣
嵣嵣嵣
0 1 2 3 4 5 6 7 8 9 10 11 12 13
29 30 31 32 33 34 35
嵣嵣嵣
嵣嵣嵣
OPCODE
24bit Address
Mode bits Dummy cycles (max 6)
0 1 1 0 1 0 1 1 X X X X X 18 嵣嵣嵣 2 1 0 4 0 Don’t care 嵣嵣嵣
MSB
High-Z
LSB
嵣嵣嵣
5 1 Don’t care 嵣嵣嵣
High
嵣嵣嵣
6 2 Don’t care 嵣嵣嵣
High
嵣嵣嵣
7 3 ^{Don’t care} 嵣嵣嵣
Data out
40 404
51 515
62 626
73
Byte 1
737
Byte 2
FRQO Command Sequence
CS
SCK
IO0
IO1
IO2
IO3
01
XX
MSB
IO switches from Input to Output
嵣嵣嵣
嵣嵣嵣
2345
21 22 23 24 25 26 27
嵣嵣嵣
嵣嵣嵣
24bit Address
X X X 18 嵣嵣嵣 2
High-Z
嵣嵣嵣
High
嵣嵣嵣
High
嵣嵣嵣
Mode bits Dummy cycles (max 6)
1 0 4 0 Don’t care 嵣嵣嵣
LSB
5 1 Don’t care ^{嵣嵣嵣}
6 2 Don’t care ^{嵣嵣嵣}
7 3 ^{Don’t care 嵣嵣嵣}
FRQO Command Sequence (XIP mode)
Data out
40 404
51 515
62 626
73
Byte 1
737
Byte 2
DS501-00043-2v0-E
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