MB85RQ4MLPF-G Datasheet, PDF (14/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• FRQAD (Fast Read Quad Address and Data)
The FRQAD command is similar to the FRQO command, except that it further improves throughput by
allowing input of the address bits (A23-A0) using 4 bits per SCK via 4 I/O pins (IO0 (SI), IO1 (SO), IO2 (WP)
and IO3 (HOLD)), at a maximum frequency of 108 MHz.
After driving CS low, FRQAD op-code is input to IO0. Then 24 address bits and 8 mode bits are input to
4 I/O pins for total 8 cycles, followed by dummy cycles. The 5 upper address bits are ignored. The number
of dummy cycles is defined beforehand by the frequency of SCK, and configured by the latency bit of LC1
and LC0. The op-code, the address and the mode bits are latched on the rising edge of SCK. After that,
FRAM memory cell array data are shifted out 4 bits at one time through 4 I/O pins synchronously to the
falling edge of SCK. When CS is risen, the FRQAD command is completed, otherwise it keeps on reading
with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 2 cycles
before CS rising. When it reaches the most significant address, it rolls over to the starting address, and
reading cycle keeps on infinitely.
FRQAD command cannot be issued soon after power-on. Any other command shall be issued at least once
before FRQAD command.
Address jumps can be done without the need for additional FRQAD command. This is controlled through
the setting of the Mode bits after the address sequence. This added feature, which is called “XIP mode”,
removes the need for the command sequence. If the Mode bits equal EFH or AFH, then the device remains
in FRQAD mode and the next address can be entered (after CS is raised high and then asserted low) without
requiring the FRQAD command, thus eliminating 8 cycles for the command sequence. If the Mode bits are
any value other than EFH and AFH, then the next time CS is raised high the device will be released from
FRQAD mode. After that, the device can accept SPI/Quad SPI commands. CS should not be driven high
during mode or dummy bits as this may make the mode bits indeterminate.
It is important that the I/O pins are set to high-impedance prior to the falling edge of the first data out clock.
The FRQAD command is terminated by driving CS high at any time during data output.
In QPI Mode, which is set by the EQPI command and is reset by the DQPI command, the FRQAD command
can be sent 4 bits per SCK rising edge.
CS
SCK
IO0
IO1
IO2
IO3
IO switches from Input to Output
嵣嵣嵣
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
嵣嵣嵣
OPCODE
24bit Address
Mode bits Dummy cycles (max 6)
1 1 1 0 1 0 1 1 X 16 12 8 4 0 4 0 Don’t care 嵣嵣嵣
High-Z
LSB
X 17 13 9 5 1 5 1 Don’t care 嵣嵣嵣
High
X 18 14 10 6 2 6 2 Don’t care 嵣嵣嵣
High
X X 15 11 7 3 7 3 ^{Don’t care} 嵣嵣嵣
MSB
FRQAD Command Sequence
Data out
40 404
51 515
62 626
73
Byte 1
737
Byte 2
14
DS501-00043-2v0-E