MB85RQ4MLPF-G Datasheet, PDF (5/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
■ OP-CODE
MB85RQ4ML accepts 8 kinds of SPI Mode command, 4 kinds of Quad SPI Mode command and 2 kinds
of QPI Mode command specified in op-code. Op-code is a code composed of 8 bits shown in the table
below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command
are not performed.
Mode Name
Description
Op-code Max Freq. (MHz) QPI
XIP
WREN Set Write Enable Latch
0000 0110B
108
Yes
No
WRDI Reset Write Enable Latch
0000 0100B
108
Yes
No
RDSR Read Status Register
0000 0101B
108
Yes
No
WRSR Write Status Register
SPI
READ Read
0000 0001B
108
0000 0011B
40
No
No
No
No
WRITE Write
0000 0010B
108
No
No
RDID Read Device ID
1001 1111B
108
No
No
FSTRD Fast Read Memory Code
0000 1011B
108
No
Yes
FRQO Fast Read Quad Output
0110 1011B
108*
No
Yes
Quad ^{FRQAD Fast Read Quad Address and Data 1110 1011B}
SPI _{WQD Write Quad Data}
0011 0010B
108*
108
Yes
Yes
No
No
WQAD Write Quad Address and Data
0001 0010B
108
Yes
No
EQPI Enable QPI mode
QPI
DQPI Disable QPI mode
0011 1000B
108
1111 1111B
108
No
No
Yes
No
*: The frequency when the number of dummy cycles is default value of 6 (see “■ LC MODE”).
Notes
1. “Yes”: Commands are supported in this mode, “No”: Commands are not supported.
2. FRQAD command cannot be issued as 1^st command after power-on. Any other command shall be issued
at least once before FRQAD command.
3-1. Single Input Address (3bytes)
SI= X, X, X, X, X, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
(Upper 5bit = any)
3-2. Quad Input Address (3bytes)
IO0=X, A16, A12, A8, A4, A0
IO1=X, A17, A13, A9, A5, A1
IO2=X, A18, A14, A10, A6, A2
IO3=X, X, A15, A11, A7, A3
(Upper 5bit = any)
4-1. Single I/O Data
SI (or SO)=D7, D6, D5, D4, D3, D2, D1, D0
4-2. Quad I/O Data
IO0=D4, D0
IO1=D5, D1
IO2=D6, D2
IO3=D7, D3
DS501-00043-2v0-E
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