MB85RQ4MLPF-G Datasheet, PDF (2/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
■ PIN ASSIGNMENT
HOLD (IO3)
VDD
NC
NC
NC
NC
CS
SO (IO1)
(TOP VIEW)
(FPT-16P-M24)
SCK
SI (IO0)
NC
NC
NC
NC
VSS
WP (IO2)
NC: Non connect pin
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select pin
This is an input pin to make chips select. When CS is “H” level, device is in deselect
7
CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code. The Chip Select pin is pulled up internally to the VDD pin via a resistor.
Write Protect pin except in Quad SPI mode
9
WP
(IO2)
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN bit of the status
register. See “■ WRITING PROTECT” for detail.
(Serial Data Input Output 2 in Quad SPI mode)
Hold pin except in Quad SPI mode
1
HOLD
(IO3)
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
“don’t care”. While the hold operation, CS has to be retained “L” level.
(Serial Data Input Output 3 in Quad SPI mode)
Serial Clock pin
16
SCK This is a clock input pin to input/output serial data. Inputs data are latched synchronously
to a rising edge, Outputs data occur synchronously to a falling edge.
15
SI
(IO0)
Serial Data Input pin except in Quad SPI mode
This is an input pin of serial data. This inputs op-code, addresses and writing data.
(Serial Data Input Output 0 in Quad SPI mode)
Serial Data Output pin except in Quad SPI mode
8
SO This is an output pin of serial data. Reading data of FRAM memory cell array and status
(IO1) register data are output. This is High-Z during standby.
(Serial Data Input Output 1 in Quad SPI mode)
2
VDD Supply Voltage pin
10
VSS Ground pin
* When using Quad SPI mode instructions, the SI, SO, WP and HOLD pins become bidirectional IO0, IO1, IO2
and IO3 pins.
2
DS501-00043-2v0-E