MB85RQ4MLPF-G Datasheet, PDF (15/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
CS
SCK
IO0
IO1
IO2
IO3
IO switches from Input to Output
嵣嵣嵣
0 1 2 3 4 5 6 7 8 9 10
嵣嵣嵣
24bit Address
Mode bits
X 16 12 8 4 0 4 0
LSB
X 17 13 9 5 1 5 1
Dummy cycles (max 6)
Don’t care 嵣嵣嵣
Don’t care 嵣嵣嵣
Data out
40 404
51 515
X 18 14 10 6 2 6 2
Don’t care 嵣嵣嵣
62 626
X X 15 11 7 3 7 3
MSB
Don’t care 嵣嵣嵣
73 737
Byte 1 Byte 2
FRQAD Command Sequence (XIP mode)
IO switches from Input to Output
CS
嵣嵣嵣
0 1 2 3 4 5 6 7 8 9 10 11 12
SCK
嵣嵣嵣
OPCODE
24bit Address
Mode bits
Dummy cycles (max 6)
Data out
IO0
0 1 X 16 12 8 4 0 4 0 Don’t care 嵣嵣嵣
LSB
40 404
IO1
1 1 X 17 13 9 5 1 5 1 Don’t care 嵣嵣嵣
51 515
IO2
1 0 X 18 14 10 6 2 6 2 Don’t care 嵣嵣嵣
62 626
IO3
1 1 X X 15 11 7 3 7 3 ^{Don’t care} 嵣嵣嵣
MSB
73
Byte 1
737
Byte 2
FRQAD Command Sequence (QPI mode)
DS501-00043-2v0-E
15