MB85RQ4MLPF-G Datasheet, PDF (16/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• WQD (Write Quad Data)
The WQD command is similar to the WRITE command, except that the data is input to 4 I/O pins (IO0 (SI),
IO1 (SO), IO2 (WP) and IO3 (HOLD)) at one time instead of 1 input pin (SI), at a maximum frequency of
108 MHz. The data transfer rate of the WQD command is four times higher than the WRITE command.
After driving CS low, WQD op-code and arbitrary 24 address bits are input to IO0. The 5 upper address bits
are ignored. When 8 writing data bits are input to 4 I/O pins for 2 cycles, data is written to FRAM memory
cell array. The op-code, the address and the data are latched on the rising edge of SCK. Risen CS will
terminate the WQD command. However, if you continue sending the writing data for 8 bits each in unit of 2
cycles before CS rising, it is possible to continue writing with automatic address increment. When it reaches
the most significant address, it rolls over to the starting address, and writing cycle keeps on infinitely.
CS
SCK
IO0
IO1
IO2
IO3
嵣嵣嵣
0 1 2 3 4 5 6 7 8 9 10 11 12 13
29 30 31 32 33 34 35
嵣嵣嵣
OPCODE
24bit Address
Data in
0 0 1 1 0 0 1 0 X X X X X 18 嵣嵣嵣 2 1 0 4 0
MSB
High-Z
LSB
嵣嵣嵣
51
404
515
High
嵣嵣嵣
62 626
High
嵣嵣嵣
73
Byte 1
737
Byte 2
WQD Command Sequence
16
DS501-00043-2v0-E