MB85RQ4MLPF-G Datasheet, PDF (17/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• WQAD (Write Quad Address and Data)
The WQAD command is similar to the WQD command, except that it further improves throughput by allowing
input of the address bits (A23-A0) using 4 bits per SCK via 4 I/O pins (IO0 (SI), IO1 (SO), IO2 (WP) and
IO3 (HOLD)), at a maximum frequency of 108 MHz.
After driving CS low, WQAD op-code is input to IO0. Then 24 address bits are input to 4 I/O pins for 6 cycles.
The 5 upper address bits are ignored. When 8 writing data bits are input to 4 I/O pins for 2cycles, data is
written to FRAM memory cell array. The opcode, the address and the data are latched on the rising edge of
SCK. Risen CS will terminate the WQAD command. However, if you continue sending the writing data for 8
bits each in unit of 2 cycles before CS rising, it is possible to continue writing with automatic address
increment. When it reaches the most significant address, it rolls over to the starting address, and writing
cycle keeps on infinitely.
In QPI Mode, which is set by the EQPI command and is reset by the DQPI command, the WQAD command
can be sent 4 bits per SCK rising edge.
CS
SCK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
OPCODE
24bit Address
Data in
00010010
High-Z
X 16 12 8 4 0 4 0
LSB
X 17 13 9 5 1 5 1
404
515
High
X 18 14 10 6 2 6 2 6 2 6
High
X X 15 11 7 3 7 3 7 3 7
MSB
Byte 1 ^{Byte 2}
WQAD Command Sequence
CS
SCK
IO0
IO1
IO2
IO3
0 1 2 3 4 5 6 7 8 9 10 11
OPCODE
24bit Address
Data in
1 0 X 16 12 8 4 0 4 0
LSB
404
0 1 X 17 13 9 5 1 5 1 5 1 5
0 0 X 18 14 10 6 2 6 2 6 2 6
0 0 X X 15 11 7 3 7 3 7 3 7
MSB
Byte 1 ^{Byte 2}
WQAD Command Sequence (QPI mode)
DS501-00043-2v0-E
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