MB85RQ4MLPF-G Datasheet, PDF (10/36 Pages) Fujitsu Component Limited. – 4 M (512 K × 8) Bit Quad SPI

MB85RQ4ML
• READ
The READ command reads FRAM memory cell array data. After driving CS low, READ op-code and arbitrary
24 address bits are input to SI. The 5 upper address bits are ignored. Then, 8 clock cycles are input to SCK.
SO outputs 8 data bits synchronously to the falling edge of SCK. While reading, the SI value is invalid. When
CS is risen, the READ command is completed, otherwise it keeps on reading with automatic address incre-
ment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it
reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely.
The maximum clock frequency for the READ command is 40 MHz.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39
OP-CODE
24-bit Address
0 0 0 0 0 0 1 1 X X X X X 18 17 16
543210
Invalid
MSB
High-Z
LSB MSB
Data Out _LSB
76543210
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. After driving CS low, WRITE op-code, arbitrary
24 address bits and 8 writing data bits are input to SI. The 5-bit upper address bits are ignored. When 8
writing data bits are input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE
command. However, if you continue sending the writing data for 8 bits each before CS rising, it is possible
to continue writing with automatic address increment. When it reaches the most significant address, it rolls
over to the starting address, and writing cycle keeps on infinitely. The maximum clock frequency for the
WRITE command is 108 MHz.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
OP-CODE
24-bit Address
Data In
0 0 0 0 0 0 1 0 X X X X X 18 17 16
54321076543210
MSB
High-Z
LSB MSB
LSB
10
DS501-00043-2v0-E