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MC9S12E64CPVE Datasheet, PDF (96/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide
Device User Guide — 9S12E12F8rDeGeV1s/DcVa0l1e.04Semiconductor, Inc.
$FFC2, $FFC3
Reserved
$FFC0, $FFC1
IIC Bus
I-Bit
IBCR (IBIE)
$C0
$FFBA to $FFBF
Reserved
$FFB8, $FFB9
FLASH
I-Bit
FCNFG (CCIE, CBEIE)
$B8
$FFB6, $FFB7
Standard Timer 1 channel 4
I-Bit
TIE (C4I)
$B6
$FFB4, $FFB5
Standard Timer 1 channel 5
I-Bit
TIE (C5I)
$B4
$FFB2, $FFB3
Standard Timer 1 channel 6
I-Bit
TIE (C6I)
$B2
$FFB0, $FFB1
Standard Timer 1 channel 7
I-Bit
TIE (C7I)
$B0
$FFAE, $FFAF
Standard Timer 1 overflow
I-Bit
TSCR2 (TOI)
$AE
$FFAC, $FFAD
Standard Timer 1 Pulse accumulator
overflow
I-Bit
PACTL (PAOVI)
$AC
$FFAA, $FFAB
Standard Timer 1 Pulse accumulator
input edge
I-Bit
PACTL (PAI)
$AA
$FFA8, $FFA9
Reserved
$FFA6, $FFA7
Standard Timer 2 channel 4
I-Bit
TIE (C4I)
$A6
$FFA4, $FFA5
Standard Timer 2 channel 5
I-Bit
TIE (C5I)
$A4
$FFA2, $FFA3
Standard Timer 2 channel 6
I-Bit
TIE (C6I)
$A2
$FFA0, $FFA1
Standard Timer 2 channel 7
I-Bit
TIE (C7I)
$A0
$FF9E, $FF9F
Standard Timer overflow
I-Bit
TSCR2 (TOI)
$9E
$FF9C, $FF9D
Standard Timer 2 Pulse accumulator
overflow
I-Bit
PACTL (PAOVI)
$9C
$FF9A, $FF9B
Standard Timer 2 Pulse accumulator
input edge
I-Bit
PACTL (PAI)
$9A
$FF98, $FF99
PMF Generator A Reload
I-Bit
PMFENCA (PWMRIEA)
$98
$FF96, $FF97
PMF Generator B Reload
I-Bit
PMFENCB (PWMRIEB)
$96
$FF94, $FF95
PMF Generator C Reload
I-Bit
PMFENCC (PWMRIEC)
$94
$FF92, $FF93
PMF Fault 0
I-Bit
PMFFCTL (FIE0)
$92
$FF90, $FF91
PMF Fault 1
I-Bit
PMFFCTL (FIE1)
$90
$FF8E, $FF8F
PMF Fault 2
I-Bit
PMFFCTL (FIE2)
$8E
$FF8C, $FF8D
PMF Fault 3
I-Bit
PMFFCTL (FIE3)
$8C
$FF8A, $FF8B
VREG LVI
I-Bit
CTRL0 (LVIE)
$8A
$FF88, $FF89
PWM Emergency Shutdown
I-Bit
PWMSDN(PWMIE)
$88
$FF80 to $FF87
Reserved
5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2.
Reset
Power-on Reset
External Reset
Low Voltage Reset
Clock Monitor Reset
Table 5-2 Reset Summary
Priority
1
1
1
2
Source
CRG Module
RESET pin
VREG Module
CRG Module
Vector
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
96
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