MC9S12E64CPVE Datasheet, PDF (124/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Device User Guide — 9S12E12^F8^rD^eG^eV1^s/D^cV^a0^l1^e.04^{Semiconductor, Inc.}
B.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
B.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
C_p
VDDPLL
C_s
R
Phase
XFC Pin
VCO
f_osc
1
f_ref
refdv+1
∆
K_Φ
K_V
f_vco
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure B-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K₁, f₁ and i_ch from Table B-4.
The grey boxes show the calculation for f_VCO = 50MHz and f_ref = 1MHz. E.g., these frequencies are used
for f_OSC = 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
K_V
=
(_---f--1----–_{----f--v--c---o---})
K₁ ⋅
e
K₁
⋅
1V
=
(_{---6---0-----}–_{-----5---0----})
–100 ⋅ e ^–100 = -90.48MHz/V
The phase detector relationship is given by:
K_Φ = – i_ch ⋅ K_V
= 316.7Hz/Ω
i_ch is the current in tracking mode.
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