MC9S12E64CPVE Datasheet, PDF (140/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Device User Guide — 9S12E12^F8^rD^eG^eV1^s/D^cV^a0^l1^e.04^{Semiconductor, Inc.}
B.7.2 ATD Operating Characteristics - 3.3V Range
The Table B-11 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-11 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V_DDA <= 3.3V+10%
Num C
Rating
Symbol Min
Typ
Max Unit
Reference Potential
1D
Low
High
V_RL
V_RH
V_SSA
V_DDA/2
V_DDA/2
V
V_DDA
V
2 C Differential Reference Voltage
V_RH-V_RL
3.0
3.3
3.6
V
3 D ATD Clock Frequency
f_ATDCLK
0.5
2.0
MHz
ATD 10-Bit Conversion Period
4D
Clock Cycles¹ _NCONV10
14
Conv, Time at 2.0MHz ATD Clock f_{ATDCLK TCONV10}
7
Conv, Time at 4.0MHz² ATD Clock f_ATDCLK T_CONV10
3.5
28 Cycles
14
µs
7
µs
ATD 8-Bit Conversion Period
5D
Clock Cycles⁽¹⁾ N_CONV8
12
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV8
6
26 Cycles
13
µs
6 D Recovery Time (V_DDA=3.3 Volts)
t_REC
20
µs
7 P Reference Supply current
I_REF
0.250 mA
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2. Reduced accuracy see Table B-13 and Table B-14.
B.7.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
B.7.3.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R_S specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
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