MC9S12E64CPVE Datasheet, PDF (79/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Freescale Semicon_Dd_evu_icc_et_Uo_ser_r,_GI_un_idc_e._{— 9S12E128DGV1/D V01.04}
Pin Name
Function 1
Pin Name
Function 2
Pin Name Power
Function 3 Domain
Internal Pull
Resistor
CTRL Reset State
Description
PQ[6:4]
PQ[3:0]
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
PT[7:4]
PT[3:0]
PU[7:6]
PU[5:4]
PU[3:0]
IS[6:4]
FAULT[3:0]
SS
SCK
MOSI
MISO
TXD1
RXD1
TXD0
RXD0
IOC1[7:4]
IOC0[7:4]
—
PW1[5:4]
IOC2[7:4]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PW1[3:0]
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PERQ/
PPSQ
PERQ/
PPSQ
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERT/
PPST
PERT/
PPST
PERU/
PPSU
PERU/
PPSU
PERU/
PPSU
Disabled Port Q I/O Pins, IS[6:4] input
Disabled Port Q I/O Pins, Fault[3:0] input
Up
Port S I/O Pin, SPI SS signal
Up
Port S I/O Pin, SPI SCK signal
Up
Port S I/O Pin, SPI MOSI signal
Up
Port S I/O Pin, SPI MISO signal
Up
Port S I/O Pin, SCI1 transmit signal
Up
Port S I/O Pin, SCI1 receive signal
Up
Port S I/O Pin, SCI0 transmit signal
Up
Port S I/O Pin, SCI0 receive signal
Disabled Port T I/O Pins, timer (TIM1)
Disabled Port T I/O Pins, timer (TIM0)
Disabled Port U I/O Pins
Disabled Port U I/O Pins, PWM outputs
Disabled Port U I/O Pins, timer (TIM2), PWM outputs
NOTES:
1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For example,
in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to the S12
MEBI Block Guide for PEAR register details.
NOTE: Signals shown in bold are not available in the 80 pin package.
NOTE: If the port pins are not bonded out in the chosen package the user should initialize the
registers to be inputs with enabled pull resistance to avoid excess current consumption.
This applies to the following pins:
(80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4]
79
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