MC9S12E64CPVE Datasheet, PDF (91/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
Core Clock
HCS12 CORE
BDM CPU
MEBI MMC
INT DBG
EXTAL
OSC CRG ^{Bus Clock}
XTAL
Oscillator Clock
Flash
RAM
ATD
DAC
IIC
PIM
PMF
PWM
SCI0, SCI1, SCI2
SPI
TIM0, TIM1, TIM2
VREG
Figure 3-1 Clock Connections
Table 3-1Clock Selection Based on PE7
PE7 = XCLKS
Description
1
Colpitts Oscillator selected
0
Pierce Oscillator/external clock selected
91
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