MC9S12E64CPVE Datasheet, PDF (136/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Device User Guide — 9S12E12^F8^rD^eG^eV1^s/D^cV^a0^l1^e.04^{Semiconductor, Inc.}
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
1
2
12
4
4
12
9
see
note
SLAVE MSB OUT
7
5
6
MSB IN
11
BIT 6 . . . 1
BIT 6 . . . 1
NOTE: Not defined!
3
13
13
8
SLAVE LSB OUT
LSB IN
Figure B-7 SPI Slave Timing (CPHA=1)
In Table B-9 the timing characteristics for slave mode are listed.
Table B-9 SPI Slave Mode Timing Characteristics
Num C
Characteristic
1
P SCK Frequency
1
P SCK Period
2
D Enable Lead Time
3
D Enable Lag Time
4
D Clock (SCK) High or Low Time
5
D Data Setup Time (Inputs)
6
D Data Hold Time (Inputs)
7
D
Slave Access Time (time to data
active)
8
D Slave MISO Disable Time
9
D Data Valid after SCK Edge
10
D Data Valid after SS fall
11
D Data Hold Time (Outputs)
12
D Rise and Fall Time Inputs
13
D Rise and Fall Time Outputs
NOTES:
1. t_bus added due to internal synchronization delay
Symbol
f_sck
t_sck
t_lead
t_lag
t_wsck
t_su
t_hi
t_a
t_dis
t_vsck
t_vss
t_ho
t_rfi
t_rfo
Min
DC
4
4
4
4
8
8
—
—
—
—
20
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
1/4
∞
—
—
—
—
—
20
22
30 + t_bus ¹
30 + t_bus ¹
—
8
8
Unit
f_bus
t_bus
t_bus
t_bus
t_bus
ns
ns
ns
ns
ns
ns
ns
ns
ns
136
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