MC9S12E64CPVE Datasheet, PDF (133/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Freescale Semicon_Dd_evu_icc_et_Uo_ser_r,_GI_un_idc_e._{— 9S12E128DGV1/D V01.04}
B.6 SPI Characteristics
This section provides electrical parametrics and ratings for the SPI.
In Table B-7 the measurement conditions are listed.
Table B-7 Measurement Conditions
Description
Drive mode
Load capacitance C_LOAD,
on all outputs
Thresholds for delay
measurement points
Value
full drive mode
50
(20% / 80%) VDDX
Unit
—
pF
V
B.6.1 Master Mode
In Figure B-4 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
2
1
12
4
4
12
5
6
MSB IN²
BIT 6 . . . 1
MOSI
(OUTPUT)
10
MSB OUT²
9
BIT 6 . . . 1
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
13
3
13
LSB IN
11
LSB OUT
Figure B-4 SPI Master Timing (CPHA=0)
In Figure B-5 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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