MC9S12E64CPVE Datasheet, PDF (126/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Device User Guide — 9S12E12^F8^rD^eG^eV1^s/D^cV^a0^l1^e.04^{Semiconductor, Inc.}
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-3.
0
1
t_min1
t_nom
t_max1
2
3
t_minN
t_maxN
N-1
N
Figure B-3 Jitter Definitions
The relative deviation of t_nom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
J(N)
=

max_

1 – ^t-N-m-----_â‹^a---t^x-_n--⁽--_o-N--_m---⁾ ,
1
–
N-t--^m---⋅^-i--nt--_n^-(--_o^-N---_m^-)-



For N < 100, the following equation is a good fit for the maximum jitter:
J(N)
=
---j-¹---
N
+
j₂
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