MC9S12E64CPVE Datasheet, PDF (139/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

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B.7 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the
ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
B.7.1 ATD Operating Characteristics - 5V Range
The Table B-10 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-10 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1D
Low VRL
High _VRH
VSSA
VDDA/2
VDDA/2 V
VDDA
V
2 C _{Differential Reference Voltage}¹
VRH-VRL 4.75
5.0
5.25
V
3 D ATD Clock Frequency
f_ATDCLK
0.5
ATD 10-Bit Conversion Period
4D
Clock Cycles² _NCONV10
14
Conv, Time at 2.0MHz ATD Clock f_{ATDCLK TCONV10}
7
Conv, Time at 4.0MHz³ ATD Clock f_ATDCLK T_CONV10
3.5
2.0
MHz
28 Cycles
14
µs
7
µs
ATD 8-Bit Conversion Period
5D
Clock Cycles⁽¹⁾ N_CONV8
12
Conv, Time at 2.0MHz ATD Clock f_ATDCLK T_CONV8
6
26 Cycles
13
µs
6 D Stop Recovery Time (V_DDA=5.0 Volts)
t_SR
20
µs
7 P Reference Supply current
I_REF
0.375 mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
3. Reduced accuracy see Table B-13 and Table B-14.
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