MC9S12E64CPVE Datasheet, PDF (135/156 Pages) Freescale Semiconductor, Inc – MC9S12E-Family Device User Guide

Freescale Semicon_Dd_evu_icc_et_Uo_ser_r,_GI_un_idc_e._{— 9S12E128DGV1/D V01.04}
B.6.2 Slave Mode
In Figure B-6 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
2
SCK
(CPOL = 1)
(INPUT)10
7
1
12
4
4
12
9
MISO
(OUTPUT)
see
note
SLAVE MSB ^{BIT 6 . . . 1}
MOSI
(INPUT)
5
6
MSB IN
BIT 6 . . . 1
NOTE: Not defined!
13 3
13
8
11
11
SLAVE LSB OUT
SEE
NOTE
LSB IN
Figure B-6 SPI Slave Timing (CPHA=0)
In Figure B-7 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
135
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