MC9S12P128_10 Datasheet, PDF (84/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Port Integration Module (S12PPIMV1)
Table 2-30. DDRM Register Field Descriptions (continued)
Field
Description
2
DDRM
Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1
DDRM
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN forces the I/O state to be an output. In this case the data direction bit will not change.
0
DDRM
1 Associated pin is configured as output
0 Associated pin is configured as input
Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN forces the I/O state to be an input. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.35 Port M Reduced Drive Register (RDRM)
Address 0x0253
7
R
0
W
Reset
0
1. Read: Anytime
Write: Anytime
6
5
4
3
2
0
RDRM5
RDRM4
RDRM3
RDRM2
0
0
0
0
0
Figure 2-33. Port M Reduced Drive Register (RDRM)
Access: User read/write⁽¹⁾
1
0
RDRM1
RDRM0
0
0
Table 2-31. RDRM Register Field Descriptions
Field
Description
5-0
RDRM
Port M reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
S12P-Family Reference Manual, Rev. 1.13
84
Freescale Semiconductor