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MC9S12P128_10 Datasheet, PDF (193/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers | |||
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S12S Debug Module (S12SDBGV2)
S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding
OR forks as shown in red this scenario is possible.
Figure 6-36. Scenario 7
M01
SCR1=1101
SCR2=1100
State1
M1
State2
M2
SCR3=1101
State3
M12 Final State
M0
M02
On simultaneous matches the lowest channel number has priority so with this conï¬guration the forking
from State1 has the peculiar effect that a simultaneous match0/match1 transitions to ï¬nal state but a
simultaneous match2/match1transitions to state2.
6.5.9 Scenario 8
Trigger when a routine/event at M2 follows either M1 or M0.
Figure 6-37. Scenario 8a
SCR1=0111
SCR2=0101
State1
M01 State2
M2
Final State
Trigger when an event M2 is followed by either event M0 or event M1
Figure 6-38. Scenario 8b
SCR1=0010
SCR2=0111
State1
M2
State2
M01 Final State
Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
193
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