MC9S12P128_10 Datasheet, PDF (512/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Electrical Characteristics
Table A-13. Pseudo Stop Current Characteristics
Conditions are: VDDR=5.5V, RTI and COP and API enabled, see Table A-8.
Num C
Rating
Symbol
Min
Typ
1 C 150°C
2 C -40°C
3 C 25°C
I_DDPS
450
I_DDPS
175
I_DDPS
200
A.2 ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
Max
Unit
µA
µA
µA
A.2.1 ATD Operating Characteristics
The Table A-14 and Table A-15 show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-14. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 3.13 V < V_DDA < 5.5 V
Num C
Rating
Symbol
Min
Typ
1 D Reference potential
Low
High
V_RL
V_SSA
—
V_RH
V_DDA/2
—
2 D Voltage difference V_DDX to V_DDA
∆_VDDX
–2.35
0
3 D Voltage difference V_SSX to V_SSA
4 C Differential reference voltage⁽¹⁾
∆_VSSX
–0.1
0
V_RH-V_RL
3.13
5.0
5 C ATD Clock Frequency (derived from bus clock via the
0.25
prescaler bus)
f_ATDCLk
6 P ATD Clock Frequency in Stop mode (internal generated
temperature and voltage dependent clock, ICLK)
0.6
1
7 D ADC conversion in stop, recovery time⁽²⁾
t_ATDSTPRC
—
—
V
ATD Conversion Period⁽³⁾
12 bit resolution:
8 D _{10 bit resolution:}
8 bit resolution:
N_CONV12
20
N_CONV10
19
N_CONV8
17
Max
Unit
V_DDA/2
V_DDA
0.1
0.1
5.5
8.0
V
V
V
V
V
MHz
1.7
MHz
1.5
us
42
ATD
41
clock
39
Cycles
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
3. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
S12P-Family Reference Manual, Rev. 1.13
512
Freescale Semiconductor