MC9S12P128_10 Datasheet, PDF (222/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.14 Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
0x02F1
7
6
5
4
3
R
0
0
0
0
0
W
Reset
0
0
0
0
0
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
= Unimplemented or Reserved
2
LVDS
U
1
LVIE
0
0
LVIF
U
Figure 7-17. Low Voltage Control Register (CPMULVCTL)
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
Field
2
LVDS
1
LVIE
0
LVIF
Table 7-14. CPMULVCTL Field Descriptions
Description
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no
effect.
0 Input voltage V_DDA is above level V_LVID or RPM.
1 Input voltage V_DDA is below level V_LVIA and FPM.
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
S12P-Family Reference Manual, Rev. 1.13
222
Freescale Semiconductor