MC9S12P128_10 Datasheet, PDF (123/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Chapter 4
Interrupt Module (S12SINTV1)
Version
Number
01.02
Revision
Date
13 Sep
2007
Effective
Date
01.03
01.04
21 Nov
2007
20 May
2009
Author
Description of Changes
updates for S12P family devices:
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
added footnote about availability of “Wake-up from STOP or WAIT
by XIRQ with X bit set” feature
4.1 Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
• I bit and X bit maskable interrupt requests
• A non-maskable unimplemented op-code trap
• A non-maskable software interrupt (SWI) or background debug mode request
• Three system reset vector requests
• A spurious interrupt vector
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.1.1 Glossary
Table 4-2 contains terms and abbreviations used in the document.
Table 4-2. Terminology
Term
CCR
ISR
MCU
Meaning
Condition Code Register (in the CPU)
Interrupt Service Routine
Micro-Controller Unit
4.1.2 Features
• Interrupt vector base register (IVBR)
• One spurious interrupt vector (at address vector base¹ + 0x0080).
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
123