MC9S12P128_10 Datasheet, PDF(237/566 Page) Freescale Semiconductor, Inc – S12 Microcontrollers

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MC9S12P128_10 Datasheet, PDF (237/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

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7.4 Functional Description

S12 Clock, Reset and Power Management Unit (S12CPMU)

7.4.1 Phase Locked Loop with Internal Filter (PLL)

The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.

The REFCLK is by default the IRCCLK which is trimmed to fIRC1M_TRIM=1MHz.

If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased ï¬exibility, OSCCLK

can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]

bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock

by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,

3, 4, 5, 6,... to 32 to generate the PLLCLK.

If oscillator is enabled (OSCE=1)

If oscillator is disabled (OSCE=0)

f REF = (---R----E----F-f--OD-----SI--V-C-----+-----1---)-

fREF = fIRC1M

fVCO = 2 Ã fREF Ã (SYNDIV + 1)

If PLL is locked (LOCK=1)

f PLL = (---P----O-----S-f--T-V---D-C----I-O-V------+-----1---)

If PLL is not locked (LOCK=0) f PLL = f---V----4-C----O---

If PLL is selected (PLLSEL=1) f bus = f---P---2-L---L--

.

NOTE

Although it is possible to set the dividers to command a very high clock

frequency, do not exceed the speciï¬ed bus frequency limit for the MCU.

S12P-Family Reference Manual, Rev. 1.13

Freescale Semiconductor

237

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