MC9S12P128_10 Datasheet, PDF (276/566 Pages) Freescale Semiconductor, Inc – S12 Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 8-26. Message Buffer Organization
Offset
Address
Register
0x00X0 Identifier Register 0
0x00X1 Identifier Register 1
0x00X2 Identifier Register 2
0x00X3 Identifier Register 3
0x00X4 Data Segment Register 0
0x00X5 Data Segment Register 1
0x00X6 Data Segment Register 2
0x00X7 Data Segment Register 3
0x00X8 Data Segment Register 4
0x00X9 Data Segment Register 5
0x00XA Data Segment Register 6
0x00XB Data Segment Register 7
0x00XC
0x00XD
Data Length Register
Transmit Buffer Priority Register⁽¹⁾
0x00XE Time Stamp Register (High Byte)
0x00XF Time Stamp Register (Low Byte)
1. Not applicable for receive buffers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Figure 8-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 8-25.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation¹.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
Figure 8-24. Receive/Transmit Message Buffer — Extended Identifier Mapping
Register
Name
0x00X0
R
IDR0
W
Bit 7
ID28
6
ID27
5
ID26
4
ID25
3
ID24
2
ID23
1
ID22
Bit0
ID21
0x00X1
IDR1
R
W
ID20
ID19
ID18
SRR (=1) IDE (=1)
ID17
ID16
ID15
0x00X2
IDR2
R
W
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
0x00X3
R
IDR3
W
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
1. Exception: The transmit buffer priority registers are 0 out of reset.
S12P-Family Reference Manual, Rev. 1.13
276
Freescale Semiconductor